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| simplified application diagram 5.0 v v+ motor mcu 33887 in out out out out out out2 out1 v+ c cp pgnd agnd fs in1 en d1 in2 d2 fb a/d 33887 33887 simplified application diagram motorola semiconductor technical data ? motorola, inc. 2004 document order number: mc33887 rev 9.0, 10/2004 33887 5.0 a h-bridge with load current feedback the 33887 is a monolithic h-bridge powe r ic with a load current feedback feature making it ideal for closed-loop dc motor control. the ic incorporates internal control logic, charge pump, gate drive, and low r ds(on) mosfet output circuitry. the 33887 is able to control inductive loads with continuous dc load currents up to 5.0 a, and with peak current active limiting between 5.2 a and 7.8 a. output loads can be pulse width modulated (pwm-ed) at frequencies up to 10 khz. the load current feedback feature provides a proportional (1/375th of the load current) constant-current output suitable for monitoring by a microcontroller?s a/d inpu t. this feature facilitates the design of closed-loop torque/speed control as well as open load detection. a fault status output terminal repor ts undervoltage, short circuit, and overtemperature conditions. two independent inputs provide polarity control of two half-bridge totem- pole outputs. two disable in puts force the h-bridge outputs to tri-state (exhibit high impedance). the 33887 is parametrically specif ied over a temper ature range of -40 c t a 125 c and a voltage range of 5.0 v v+ 28 v. the ic can also be operated up to 40 v with dera ting of the specifications. features ? 5.0 v to 40 v continuous operation ? 120 m ? r ds(on) h-bridge mosfets ? ttl/cmos compatible inputs ? pwm frequencies up to 10 khz ? active current limiting (regulation) via internal constant off-time pwm (with temperature-dependent threshold reduction) ? output short circuit protection (short to v+ or short to gnd) ? undervoltage shutdown ? fault status reporting ? sleep mode with current draw 50 a (inputs floating or set to match default logic states) ? pb-free packaging designated by suffix codes vw and pnb 5.0 a h-bridge with load current feedback ordering information device temperature range (t a ) package mc33887dh/r2 -40c to 125c -40c to 125c -40c to 125c 20 hsop PC33887VW/r2 mc33887pnb/r2 36 pqfn mc33887dwb/r2 54 soicw-ep dwb suffix case 1390-01 54-terminal soicw-ep dh suffix vw (pb-free) suffix case 979-04 20-terminal hsop pnb (pb-free) suffix case 1503-01 36-terminal pqfn 33887 simplified application diagram bottom view f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33887 motorola analog integrated circuit device data 2 figure 1. 33887 simplified internal block diagram over tem pe r atu re gate drive current limit, ov ercurrent s ens e, & feedback circuit charge pump undervoltage out1 out2 fb c cp v pwr pgnd 5. 0 v regu lato r in1 in2 d1 d2 fs agnd control lo gic 80 ua ( each ) 25 ua c cp 80 a (each) 25 a over- temperature en v+ charge pump low-side current limit, short circuit sense, and current feedback circuit undervoltage protection overtemperature detection gate drive control logic 5.0 v regulator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 3 en agnd in2 d1 c cp v+ out2 out2 d2 pgnd pgnd fs v+ out1 out1 fb pgnd pgnd in1 v+ 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17 tab tab hsop terminal definitions a functional description of each terminal can be fo und in the system/application information section, page 19 . terminal terminal name formal name definition 1 agnd analog ground low-current analog signal ground. 2 fs fault status for h-bridge open drain active low fault status output requiring a pullup resistor to 5.0 v. 3 in1 logic input control 1 logic input control of out1 (i.e., in1 logic high = out1 high). 4, 5, 16 v+ positive power supply positive supply connections 6, 7 out1 h-bridge output 1 output 1 of h-bridge. 8 fb feedback for h-bridge current sensing feedback output providing ground referenced 1/375th (0.00266) of h-bridge high-side current. 9?12 pgnd power ground high-current power ground. 13 d2 disable 2 active low input used to simultaneously tr i-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 14, 15 out2 h-bridge output 2 output 2 of h-bridge. 17 c cp charge pump capacitor external reservoir capacitor connecti on for internal charge pump capacitor. 18 d1 disable 1 active high input used to simultaneously tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 19 in2 logic input control 2 logic input control of out2 (i.e., in2 logic high = out2 high). 20 en enable logic input enable control of device (i.e., en logic high = full operation, en logic low = sleep mode). tab/pad thermal interface exposed pad thermal interface exposed pad thermal interface for sinking heat from the device. note must be dc-coupled to analog ground and power ground via very low impedance path to prevent injection of s purious signals into ic substrate. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 4 d2 nc 28 27 26 25 24 23 22 21 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 pgnd pgnd pgnd pgnd pgnd pgnd in2 d1 en v+ v+ nc agnd fs v+ c cp v+ out2 out2 nc out2 out2 v+ in1 v+ out1 out1 nc out1 out1 20 fb 19 nc 10 nc 1 nc transparent top view of package pqfn terminal definitions a functional description of each terminal can be fo und in the system/application information section, page 19 . terminal terminal name formal name definition 1, 7, 10, 16, 19, 28, 31 nc no connect no internal connection to this terminal. 2 d1 disable 1 active high input used to simultaneous ly tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 3 in2 logic input control 2 logic input control of out2 (i.e., in2 logic high = out2 high). 4 en enable logic input enable control of device (i.e., en logic high = full operation, en logic low = sleep mode). 5, 6, 12, 13, 34, 35 v+ positive power supply positive supply connections. 8 agnd analog ground low-current analog signal ground. 9 fs fault status for h-bridge open drain active low fault status output requiring a pullup resistor to 5.0 v. 11 in1 logic input control 1 logic input control of out1 (i.e., in1 logic high = out1 high). 14, 15, 17, 18 out1 h-bridge output 1 output 1 of h-bridge. 20 fb feedback for h-bridge current feedback output providing ground referenced 1/375th ratio of h-bridge high-side current. 21?26 pgnd power ground high-current power ground. 27 d2 disable 2 active low input used to simultaneous ly tri-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 29, 30, 32, 33 out2 h-bridge output 2 output 2 of h-bridge. 36 c cp charge pump capacitor external reservoir capacitor connecti on for internal charge pump capacitor. pad thermal interface exposed pad thermal interface exposed pad thermal interface for sinking heat from the device. note must be dc-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into ic substrate. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 5 pgnd nc v+ v+ v+ v+ nc nc nc nc c cp d1 in2 en nc nc nc out2 out2 out2 out2 nc nc d2 pgnd pgnd pgnd pgnd nc v+ v+ v+ v+ nc nc nc nc in1 fs agnd nc nc nc nc out1 out1 out1 out1 nc nc fb pgnd pgnd pgnd 54 40 .35 34 33 32 31 30 29 28 39 38 37 36 47 46 45 44 43 42 41 51 50 49 48 53 52 1 15 20 21 22 23 24 25 26 27 16 17 18 19 8 9 10 11 12 13 14 4 5 6 7 2 3 transparent top view of package soicw-ep terminal definitions a functional description of each terminal can be fo und in the system/application information section, page 19 . terminal terminal name formal name definition 1?4, 51?54 pgnd power ground high-current power ground. 5?7, 9, 14, 19?22, 27? 29, 33?36, 41, 46, 48?50 nc no connect no internal connection to this terminal. 8 d2 disable 2 active low input used to simultaneously tri-state disable both h-bridge outputs. when d2 is logic low, both outputs are tri-stated. 10?13 out2 h-bridge output 2 output 2 of h-bridge. 15 ?18, 37?40 v+ positive power supply positive supply connections. 23 c cp charge pump capacitor external reservoir capacitor connecti on for internal charge pump capacitor. 24 d1 disable 1 active high input used to simultaneous ly tri-state disable both h-bridge outputs. when d1 is logic high, both outputs are tri-stated. 25 in2 logic input control 2 logic input control of out2 (i.e., in2 logic high = out2 high). 26 en enable logic input enable control of device (i.e., en logic high = full operation, en logic low = sleep mode). 30 agnd analog ground low-current analog signal ground. 31 fs fault status for h-bridge open drain active low fault status output requiring a pullup resistor to 5.0 v. 32 in1 logic input control 1 logic input control of out1 (i.e., in1 logic high = out1 high). 42?45 out1 h-bridge output 1 output 1 of h-bridge. 47 fb feedback for h-bridge current feedback output providing ground referenced 1/375th ratio of h-bridge high-side current. pad thermal interface exposed pad thermal interface exposed pad thermal interface for sinking heat from the device. note must be dc-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into ic substrate. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 6 . maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings supply voltage v+ 40 v input voltage (note 1) v in -0.3 to 7.0 v fs status output (note 2) v fs 7.0 v continuous current (note 3) i out 5.0 a dh suffix hsop esd voltage human body model (note 4) each terminal to agnd each terminal to pgnd each terminal to v+ each i/o to all other i/os machine model (note 5) v esd1 v esd1 v esd1 v esd1 v esd2 1000 1500 2000 2000 200 v vw suffix hsop esd voltage human body model (note 4) machine model (note 5) v esd1 v esd2 2000 200 v pqfn esd voltage human body model (note 4) machine model (note 5) v esd1 v esd2 2000 200 v soicw-ep esd voltage human body model (note 4) machine model (note 5) v esd1 v esd2 1600 200 v thermal ratings storage temperature t stg -65 to 150 c operating temperature (note 6) ambient junction t a t j -40 to 125 -40 to 150 c peak package reflow temperature during solder mounting (note 7) hsop pqfn soicw-ep t solder 220 260 240 c notes 1. exceeding the input voltage on in1, in2, en, d1, or d2 may cause a malfunction or permanent damage to the device. 2. exceeding the pullup resistor voltage on the open drain fs terminal may cause permanent damage to the device. 3. continuous current capability so long as junction temperature is 150 c. 4. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 5. esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 6. the limiting factor is junction temperat ure, taking into account the power dissi pation, thermal resistance, and heat sinking provided. brief nonrepetitive excursions of junction temperature above 150 c can be tolerated as long as durati on does not exceed 30 seconds maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.) 7. terminal soldering temperature limit is for 10 seconds maximum duration. not desi gned for immersion soldering. exceeding thes e limits may cause malfunction or permanent damage to the device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 7 thermal resistance (and p ackage dissipation) ratings (note 8) , (note 9) , (note 10) , (note 11) junction-to-board (bottom exposed pad soldered to board) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r jb ~5.0 ~4.3 ~8.0 c/w junction-to-ambient, natural conv ection, single-layer board (1s) (note 12) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r ja ~41 ~tbd ~62 c/w junction-to-ambient, natural convec tion, four-layer board (2s2p) (note 13) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r jma ~30 ~21.3 ~tbd c/w junction-to-case (exposed pad) (note 14) hsop (6.0 w) pqfn (4.0 w) soicw-ep (2.0 w) r jc ~0.5 ~0.9 ~1.5 c/w notes 8. the limiting factor is junction temperat ure, taking into account the power dissipat ion, thermal resistance, and heat sinking. 9. exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. the actual r jb (junction-to-pc board) values will vary depending on solder thicknes s and composition and copper trace thickness. maximum current at maximum die tempe rature represents ~16 w of conduction loss heating in the di agonal pair of output mosfets. therefore, the r jc -total must be less than 5.0 c/w for maximum load at 70c ambient. module thermal design must be planned accordingly. 10. thermal resistance between the die and the printed circuit boar d per jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. 11. junction temperature is a function of on-chip power dissipation, package thermal re sistance, mounting site (board) temperatu re, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. per semi g38-87 and jedec jesd51-2 with t he single-layer board (jesd51-3) horizontal. 13. per jedec jesd51-6 with the board horizontal. 14. indicates the average thermal resistance between the die and the exposed pad surface as measured by the cold plate method (m il spec- 883 method 1012.1) with the cold plate temperature used for the case temperature. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. rating symbol value unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 8 static electrical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power supply operating voltage range (note 15) v+ 5.0 ? 40 v sleep state supply current (note 16) i out = 0 a, v en = 0 v i q(sleep) ?2550 a standby supply current i out = 0 a, v en = 5.0 v i q(standby) ??20 ma threshold supply voltage switch-off switch-on hysteresis v+ (thres-off) v+ (thres-on) v+ (hys) 4.15 4.5 150 4.4 4.75 ? 4.65 5.0 ? v v mv charge pump charge pump voltage v+ = 5.0 v 8.0 v v+ 40 v v cp -v+ 3.35 ? ? ? ? 20 v control inputs input voltage (in1, in2, d1, d2 ) threshold high threshold low hysteresis v ih v il v hys 3.5 ? 0.7 ? ? 1.0 ? 1.4 ? v input current (in1, in2, d1) v in - 0.0 v i inp -200 -80 ? a input current (d2 , en) v d2 = 5.0 v i inp ?25100 a notes 15. specifications are characte rized over the range of 5.0 v v+ 28 v. operation >28 v will cause some parameters to exceed listed min/max values. refer to typical operating curves to extrapolate values for operation >28 v but 40 v. 16. i q( sleep ) is with sleep mode function enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 9 static electrical charac teristics (continued) characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. ty pical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power outputs (out1, out2) output on-resistance (note 17) 5.0 v v+ 28 v, t j = 25c 8.0 v v+ 28 v, t j = 150c 5.0 v v+ 8.0 v, t j = 150c r ds(on) ? ? ? 120 ? ? ? 225 300 m ? active current limiting threshold (via internal constant off-time pwm) on low-side mosfets (note 18) i lim 5.2 6.5 7.8 a high-side short circuit detection threshold i sch 11 ? ? a low-side short circuit detection threshold i scl 8.0 ? ? a leakage current (note 19) v out = v+ v out = ground i out( leak ) ? ? 100 30 200 60 a output mosfet body diode forward voltage drop i out = 3.0 a v f ??2.0 v overtemperature shutdown thermal limit hysteresis t lim t hys 175 10 ? ? 225 30 c high-side current sense feedback feedback current i out = 0 ma i out = 500 ma i out = 1.5 a i out = 3.0 a i out = 6.0 a i fb ? 1.07 3.6 7.2 14.4 ? 1.33 4.0 8.0 16 600 1.68 4.62 9.24 18.48 a ma ma ma ma fault status (note 20) fault status leakage current (note 21) v fs = 5.0 v i fs ( leak ) ??10 a fault status set voltage (note 22) i fs = 300 a v fs (low) ??1.0 v notes 17. output-on resistance as measured from output to v+ and ground. 18. active current limitation applies only for the low-side mosfets. 19. outputs switched off with d1 or d2 . 20. fault status output is an open drain output requiring a pullup resistor to 5.0 v. 21. fault status leakage current is measured with fault status high and not set. 22. fault status set voltage is measured with fault status low and set with i fs = 300 a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 10 dynamic electrical characteristics characteristics noted under conditions 5.0 v v+ 28 v and -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (note 23) f pwm ?10?khz maximum switching frequency during active current limiting (note 24) f max ??20khz output on delay (note 25) v+ = 14 v t d (on) ??18 s output off delay (note 25) v+ = 14 v t d (off) ??18 s i lim output constant-off time for low-side mosfets (note 26), (note 27) t a 15 20.5 26 s i lim blanking time for low-side mosfets (note 28) , (note 27) t b 12 16.5 21 s output rise and fall time (note 29) v+ = 14 v, i out = 3.0 a t f , t r 2.0 5.0 8.0 s disable delay time (note 30) t d(disable) ??8.0 s power-on delay time (note 31) t pod ?1.05.0ms wake-up delay time (note 31) t wud ?1.05.0ms output mosfet body diode reverse recovery time (note 32) t rr 100 ? ? ns notes 23. the outputs can be pwm-controlled from an external source. this is typically don e by holding one input high while applying a pwm pulse train to the other input. the maximum pwm frequency obtainable is a compromise between switching losses and switching frequency . see typical switching waveforms, figures 11 through 18 , pp. 15?16. 24. the maximum switching frequency during active current limiting is internally implemen ted. the internal current limit circuit ry produces a constant-off-time pulse-width modulation of the output current. the output load?s inductance, capacitance, and resistance chara cteristics affect the total switching period (off-time + on-time) and thus the pwm frequency during current limit. 25. output delay is the time duration from the midpoint of the in1 or in2 input signal to the 10% or 90% point (dependent on the transition direction) of the out1 or out2 signal. if the output is transiti oning high-to-low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. if the output is transiti oning low-to-high, the delay is from the midpoint of the inpu t signal to the 10% point of the output response signal. see figure 2 , page 11. 26. i lim output constant-off time is the time during which the internal constant-off time pwm current regulation circuit has tri-stated the output bridge. 27. load currents ramping up to the current regulation threshold become limited at the i lim value. the short circuit currents possess a di/dt that ramps up to the i sch or i scl threshold during the i lim blanking time, registering as a short circ uit event detection and causing the shutdown circuitry to force the output into an immediate tri-state latch-off. see figures 6 and 7 , page 12. operation in current limit mode may cause junction temperatures to rise. junction temperatures above ~160 c will cause the output current limit th reshold to progressively ?fold back?, or decrease with temperature, until ~175 c is reached, after which the t lim thermal latch-off will occur. permissible operation within this foldback region is limited to nonr epetitive transient events of durat ion not to exceed 30 seconds. see figure 5 , page 11. 28. i lim blanking time is the time during which t he current regulation threshold is ignored so that the short-circuit detection thresho ld comparators my have time to act. 29. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal. see figure 4 , page 11. 30. disable delay time is the time duration from the midpoint of the d (disable) input signal to 10% of the output tri-state res ponse. see figure 3 , page 11. 31. parameter has been characteri zed but not production tested. 32. parameter is guaranteed by design but not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 11 timing diagrams figure 2. output delay time figure 3. disable delay time figure 4. output switching time figure 5. active current limiting versus temperature (typical) time 0 5.0 0 v pwr t d(on) 50% 90% 50% 10% v i n 1 , i n 2 ( v ) t d(off) v o u t 1 , 2 ( v ) ? 0 v 5.0 v 0 ? t r 0 v pwr 90% 10% v o u t 1 , 2 ( v ) 10% 90% t f i m a x , o u t p u t c u r r e n t ( a ) 6.6 2.5 160 175 thermal shutdown t j , junction temperature ( o c) i lim , 6.5 i lim , current (a) 4.0 operation within this region must be 150 limited to nonrepetitive events not to exceed 30 seconds f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 12 figure 6. operating states figure 7. example short circuit detection detail on low-side mosfet active current limiting >8a 6.5 short circuit detection threshold typical current limit threshold hard short detect ion and latch-off 0 in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 [1] [0] [1] [0] [1] [0] [1] [0] outputs tri-stated outputs tri-stated outputs operation (per input control condition) time sf , logic out d2 , logic in d1, logic in in n , logic in i load , output current (a) high current load being regulated via constant-off-time pwm moderate current load on low-side mosfet overcurrent minimum threshold t a t b 8.0 time i l o a d , o u t p u t c u r r e n t ( a ) typical pwm load current limiting waveform hard output short latch-off t a = tristate output off time t b = current limit blank time 6.5 hard short detect ion short circuit detect threshold t a = output constant-off time t b = output blanking time i scl short circuit detection threshold i out , current (a) typical current limiting waveform t b 5.0 t a 8.0 hard short occurs. hard short is detected during t b i lim blanking time t on 0.0 and output is latched-off. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 13 electrical performance curves figure 8. typical high-side r ds(on) versus v+ figure 9. typical low-side r ds(on) versus v+ 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 volts ohms 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 0.13 0.128 0.126 0.124 0.122 0.12 ohms v pwr ohms volts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 14 figure 10. typical quiescent supply current versus v+ 5911 7131519 37 33 35 39 27 41 29 17 21 23 25 31 5.0 4.0 3.0 2.0 1.0 0.0 ohms v pwr 6.0 7.0 8.0 9.0 milliamperes volts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 15 typical switching waveforms important for all plots, the following applies: ? ch2=2.0 a per division ?l load =533 h @ 1.0 khz ?l load =530 h @ 10.0 khz ?r load =4.0 ? figure 11. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 10% figure 12. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 1.0 khz, and duty cycle of 50% figure 13. output voltage and current vs. input voltage at v+ = 34 v, pmw frequency of 1.0 khz, and duty cycle of 90%, showing device in current limiting mode figure 14. output voltage and current vs. input voltage at v+ = 22 v, pmw frequency of 1.0 khz, and duty cycle of 90% v+=24 v f pwm =1.0 khz duty cycle=10% output voltage (out1) i out input voltage (in1) v+=24 v f pwm = 1.0 khz duty cycle = 50% output voltage (out1) i out input voltage (in1) v+=34 v f pwm =1.0 khz duty cycle=90% output voltage (out1) i out input voltage (in1) v+=22 v f pwm =1.0 khz duty cycle=90% output voltage (out1) i out input voltage (in1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 16 figure 15. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 50% figure 16. output voltage and current vs. input voltage at v+ = 24 v, pmw frequency of 10 khz, and duty cycle of 90% figure 17. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 50% for a purely resistive load figure 18. output voltage and current vs. input voltage at v+ = 12 v, pmw frequency of 20 khz, and duty cycle of 90% for a purely resistive load v+=24 v f pwm =10 khz duty cycle=50% output voltage (out1) i out input voltage (in1) v+=24 v f pwm =10 khz duty cycle=90% output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=50% output voltage (out1) i out input voltage (in1) v+=12 v f pwm =20 khz duty cycle=90% output voltage (out1) i out input voltage (in1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 17 table 1. truth table the tri-state conditions and the faul t status are reset using d1 or d2 . the truth table uses the foll owing notations: l = low, h = high, x = high or low, and z = high impedance (all output power transistors are switched off). device state input conditions fault status flag output states en d1 d2 in1 in2 fs out1 out2 forward h l h h l h h l reverse hlhlh h l h freewheeling low h l h l l h l l freewheeling high h l h h h h h h disable 1 (d1) h h x x x l z z disable 2 ( d2 ) hxlxx l z z in1 disconnected h l h z x h h x in2 disconnected h l h x z h x h d1 disconnected h z x x x l z z d2 disconnected hxzxx l z z undervoltage (note 33) hxxxx l z z overtemperature (note 34) hxxxx l z z short circuit (note 34) hxxxx l z z sleep mode en l x x x x h z z en disconnected z x x x x h z z notes 33. in the case of an undervoltage condition, the outputs tri-state and the fault status is set logic low. upon undervoltage rec overy, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 34. when a short circuit or overtemperature condition is detected, the power outputs are tri-st ate latched-off independent of th e input signals and the fault status flag is set logic low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 18 system/application information introduction numerous protection and operational features (speed, torque, direction, dynamic braking, pwm control, and closed- loop control), in addition to the 5.0 a current capability, make the 33887 a very attractive, cost-effective solution for controlling a broad range of small dc motors. in addition, a pair of 33887 devices can be used to control bipolar stepper motors. the 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding ac currents. as shown in figure 1 , simplified internal block diagram, page 2, the 33887 is a fully prot ected monolithic h-bridge with enable, fault status reporting, and high-side current sense feedback to accommodate closed-loop pwm control. for a dc motor to run, the input conditions need be as follows: enable input logic high, d1 input logic low, d2 input logic high, fs flag cleared (logic high), one in logic low and the other in logic high (to define output pol arity). the 33887 can execute dynamic braking by simultaneously turning on either both high- side mosfets or both low-side mosfets in the output h-bridge; e.g., in1 and in2 logic high or in1 and in2 logic low. the 33887 outputs are capable of providing a continuous dc load current of 5.0 a from a 40 v v+ source. an internal charge pump supports pwm frequencies to 10 khz. an external pullup resistor is required at the fs terminal for fault status reporting. the 33887 has an analog feedback (current mirror) output terminal (the fb terminal) that provides a constant-current source ratioed to the active high-side mosfet. this can be used to provide ?real time? monitoring of load current to facilitate closed-loop operation for motor speed/torque control. two independent inputs (in1 and in2) provide control of the two totem-pole half-bridge outputs. two disable inputs (d1 and d2 ) provide the means to force the h-bridge outputs to a high- impedance state (all h-bridge switches off). an en terminal controls an enable function that allows the 33887 to be placed in a power-conserving sleep mode. the 33887 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latch-off, and overtemperature latch-off. an undervoltage shutdown, output short-circuit latch-off, or overtemperature latch-off fault condition will cause the outputs to turn off (i.e., become high impedance or tri-stated) and t he fault output flag to be set low. either of the disable inputs or v+ must be ?toggled? to clear the fault flag. active current limiting is accomplished by a constant off- time pwm method employing active current limiting threshold triggering. the active current lim iting scheme is unique in that it incorporates a junction temp erature-dependent current limit threshold. this means the active current limiting threshold is ?ramped down? as the junction temperature increases above 160 c, until at 175 c the current will have been decreased to about 4.0 a. above 175 c, the overtemperature shutdown (latch-off) occurs. this combi nation of features allows the device to remain in operation for 30 seconds at junction temperatures above 150 c for nonrepetitive unexpected loads. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 19 functional terminal description pgnd and agnd power and analog ground terminals should be connected together with a very low impedance connection. v+ v+ terminals are the power supply inputs to the device. all v+ terminals must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between terminals. v+ terminals have an undervoltage threshold. if the supply voltage drops below a v+ undervol tage threshold, the output power stage switches to a tri-stat e condition and the fault status flag is set and the fault status terminal voltage switched to a logic low. when the supply voltag e returns to a level that is above the threshold, the power stage automatically resumes normal operation according to t he established condition of the input terminals and the fault stat us flag is automatically reset logic high. fault status (fs ) the fs terminal is the device fault status output. this output is an active low open drain structure requiring a pullup resistor to 5.0 v. refer to table 1, truth table , page 17. in1, in2, d1, and d2 these terminals are input contro l terminals used to control the outputs. these terminals are 5.0 v cmos-compatible inputs with hysteresis. the in 1 and in2 independently control out1 and out2, respectively. d1 and d2 are complementary inputs used to tri-state disable the h-bridge outputs. when either d1 or d2 is set (d1 = logic high or d2 = logic low) in the disable state, outputs out1 and out2 are both tri- state disabled; however, the rest of the device circuitry is fully operational and the supply i q( standby) current is reduced to a few milliamperes. refer to table 1, truth table , and static electrical characteristics table, page 8. out1 and out2 these terminals are the out puts of the h-bridge with integrated output mosfet body diodes. the bridge output is controlled using the in1, in2, d1, and d2 inputs. the low-side mosfets have active current limiting above the i lim threshold. the outputs also have thermal shutdown (tri-state latch-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) incorporated to de tect currents that are higher than current limit is activated at each output activation to facilitate hard short detection (see figure 7 , page 12). c cp a filter capacitor (up to 33 nf) can be connected from the charge pump output terminal and pgnd. the device can operate without the external capacitor, although the c cp capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and pwm frequency. en the en terminal is used to place the device in a sleep mode so as to consume very low currents. when the en terminal voltage is a logic low state, th e device is in the sleep mode. the device is enabled and fully operational when the en terminal voltage is logic high. an internal pulldown resistor maintains the device in sleep mode in the event en is driven through a high impedance i/o or an unpowered microcontroller, or the en input becomes disconnected. fb the 33887 has a feedback output (fb) for ?real time? monitoring of h-bridge high-side current to facilitate closed- loop operation for motor speed and torque control. the fb terminal provides curr ent sensing feedback of the h-bridge high-side drivers. wh en running in the forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this terminal. through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can ?read? the current proportional voltage with its analog-to-digital converter (adc). this is intended to provide the user with motor current feedback for motor torque control. the resistance range for the linear operation of the fb terminal is 100 motorola analog integrated circuit device data 33887 21 applications figure 21 shows a typical application schematic. for precision high-current applic ations in harsh, noisy environments, the v+ by-pass capacitor may need to be substantially larger. figure 21. 33887 typical application schematic motor agnd out1 fb pgnd v+ c cp out2 en d2 d1 fs in1 in2 33 nf 47 f v+ 100 ? 1.0 f 33887 + + fb in2 in1 fs d1 d2 en dc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 22 package dimensions gauge plane detail y (1.600) l w w q l1 a1 ccc c ccc d d seating plane datum plane a a2 detail y c h bottom view d1 e3 e4 exposed heatsink area dim min max millimeters a 3.100 3.350 a1 0.050 bsc a2 3.100 3.250 d 15.800 16.000 d1 12.270 12.470 d2 0.900 1.100 e 13.950 14.450 e1 10.900 11.100 e2 2.500 2.700 e3 7.000 7.200 l 0.840 1.100 l1 0.350 bsc b 0.400 0.520 b1 0.400 0.482 c 0.230 0.310 c1 0.230 0.280 e 1.270 bsc h --- 1.100 q 0 8 aaa 0.200 bbb 0.200 e4 2.700 2.900 ccc 0.100 notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane -h-. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.178 total in excess of the b dimension at maximum material condition. 6. datums -a- and -b- to be determined at datum plane -h-. 7. dimension d does not include tiebar protrusions. allowable tiebar protrusions are 0.150 per side. x 45? h e1 e d e 18x e/2 b m bbb c 20 11 10 1 e2 d2 a b pin one id section w-w b c1 b1 c a m aaa c dh suffix vw (pb-free) suffix 20-terminal hsop plastic package case 979-04 issue c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 23 m m detail g pin 1 index area 9 9 0.1 c 2x c 0.1 2x 0.1 a cb 3.2 36 28 19 10 1 2 pin 1 index a b 6.5 5.5 6.5 5.5 3.2 0.1 a cb detail n 0.4 1.08 0.94 32x 0.60 0.45 32x 0.1 m a cb 0.05 m c view m m 4.3 40x (0.175) 4.3 2x 40x 0.9 0.7 0.37 0.23 4 places 0.1 m a cb 0.05 m c detail n corner configuration 2.2 2.0 2.20 1.95 0.05 0.00 (0.8) (0.55) detail g view rotated 90? cw c 0.1 0.05 c 4 c seating plane 0.6 0.4 2x notes: 1. 2. 3. 4. all dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. the complete jedec designator for this package is: f-pqfp-n. coplanarity applies to leads and corner leads. pnb (pb-free) suffix 36-terminal pqfn non-leaded package case 1503-01 issue o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 24 17.8 7.4 1 27 28 54 b 9 5 c 7.6 18.0 9 4 10.3 5.15 0.3 a b c 2x 27 tips bb pin 1 index 0.10 a 2.35 seating plane 0.65 a 54x 52x 2.65 0.9 section b-b r0.08 min 0.1 0.0 0.5 0? 8? 0? 0.25 gauge plane min (1.43) notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums b and c to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.46 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead shall not less than 0.07 mm. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1 mm and 0.3 mm from the lead tip. 9. the package top may be smaller than the package bottom. this dimension is determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and inter-lead flash, but including any mismatch between the top and bottom of the plastic body. a a c c (0.29) 0.38 0.30 (0.25) plating base metal section a-a rotated 90? clockwise 8 0.25 0.22 m 0.13 c ab 6 4.8 4.3 0.30 c ab 4.8 4.3 0.30 c ab view c-c dwb suffix 54-terminal soicw exposed pad plastic package case 1390-01 issue b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 25 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 33887 motorola analog integrated circuit device data 26 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola analog integrated circuit device data 33887 27 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com mc33887 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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